Class-E PA Appendix

On this page we give a little more background information for the design as well as the design process used for the Class-E Power amplifier.

Below is a list of all the topics we cover in this page. Click on any of these links to go to that section.

background and purpose of the class-e pa

The class-E Power Amplifier (PA) is a switch mode PA which has a potential theoretical efficiency of approximately 100%. Being a switching mode PA, the Power FET is used as an ON-OFF switch. Using the basic switching mode PA with the circuit topology seen in image (a) below, we can only achieve a maximum efficiency of ~81% due to losses from all other odd harmonics besides the fundamental. To overcome this efficiency limitation, first a series resonator (LC) is added at the output to act like a short at the fundamental frequency, and an open at all other harmonics. Next a capacitor (Cp) placed in parallel with the switch to store charge when the switch is closed and to provide current when it is open. Finally an inductor (Ls) is put in series with the resonator to phase shift the current to ensure it is 0 (zero) Amps at the switch closing point. The resulting Class-E circuit topology is shown in image (b).

The Class-E PA was used within our Magnetically Coupled Resonant, Wireless Power Transmission system (or MCR-WPT system) based on the now obsolete Rezence WPT standard (superseded by Qi). This is mainly due to the high efficiency of the Class-E PA which results in most of the power going to the Transmitter coils of the Rezence system. Also, the fundamental load of the Class E PA is inductive, which is good for driving WPT coils.

For more detailed information on the basic theory of the Class-E PA, the design methodology used, design specifications and results, check out section 2.3 of the thesis. For more brief overview of the Rezence WPT standard, see section 1.1.1 The thesis can be obtained from the Ryerson University library by clicking the button below.

Design Component Values

Class-E Measurement Results

Parameter	Value (experimental value)
Ideal Class Parameters
V_DC	36V
C_p-external	68pF
C_p-internal	68pF
L_shift+L_res	15uH
C_res	39pF
Output Matching Network
C2	470pF
C3	620pF (150+470)
L3	500nH
Input Matching Network
C6	2750pF (1600+820+330)
C7	10nF
C8	220pF
L6	500nH
Miscellaneous
Choke Inductors (L1 and L4)	15uH
Input bias voltage	3V
Input Power	2Watts
Input impedance	27Ω

simulation and prototype efficiency differences

The main source of the efficiency decrease was due to the 39pF C_res capacitor with 2% tolerance used within the prototype. It was found to have a measured capacitance of 40pF. A harmonic balance simulation with this value shows efficiency drops by more than 10%.